As speed requirements of computer processing units have increased, systems employing greater numbers of parallel memory modules have been developed. One such system, Illiac IV, has in the order of 64 parallel memories, see U.S. Pat. No. 3,537,074, issued Oct. 27, 1970 to R. A. Stokes et al., and assigned to the assignee of the present invention.
Parallel memory systems generally suffer however from unavoidable memory conflicts. Severe storage problems frequently arise in performing matrix computations. Consider for example, a typical two-dimensional matrix having its elements stored column-by-column in a parallel memory array. Under such a storage system, row, forward diagonal and reverse diagonal elements may be accessed in parallel. However, column elements must be accessed serially out of each memory. Thus a memory conflict arises which limits the processing capability of the parallel memory system.
Other storage systems permit parallel access to a matrix column but may cause a conflict for row, diagonal or other matrix vector access. The conflict problem has been studied, see Budnik and Kuck, "The Organization and Use of Parallel Memories", IEEE TRANSACTIONS ON COMPUTERS, December 1971, pages 1566-1569, and "Access and Alignment of Data in an Array Processor", D. H. Lawrie, IEEE TRANSACTIONS ON COMPUTERS, December 1975. However, attempts to solve the conflict problem generally lead to a relatively complex memory storage system and tend to increase the complexity of aligning the plurality of parallel memories with the associated plurality of arithmetic units or processors.